In the manufacture and assembly of electronic devices, flip chip technology is increasingly popular as a high-density interconnection technique for mounting and electrically connecting semiconductor dies (or “chips”) on redistribution substrates. Interconnection substrates for these techniques include silicon, ceramic, and flexible plastic, as well as printed circuit boards. The flip chip technique presents solder pads (typically utilizing solder balls) on the surface of the substrate.
Flip chip interconnections provide the shortest electrical connecting paths, and therefore the highest electrical performance and speed. Flip chip interconnections also accommodate the greatest number of chips and chip connections within a given space because the flip chip technique can present area arrays at any location, including the center area of the die, as well as or in addition to the periphery of the die.
The adoption of both a peripheral array and a center area array together in the same flip chip interconnection facilitates even further shrinking of package modules, and simultaneously provides better electrical performance due to lower inductance and cross talk from the direct solder ball connections.
Flip chip is therefore increasingly the interconnect method of choice for high performance semiconductor devices, such as application specific integrated circuits (“ASICs”).
Input/output (“I/O”) pads for flip-chip interconnection must have a final surface finish of solder-wettable metal. Since the metal finish ends up under the solder balls, or “solder bumps”, it is referred to as under-bump metallization (“UBM”). A typical UBM metal stack consists of an adhesion layer (on the bottom), an optional barrier layer (in the middle), and one or more wetting layers (on the top). Structures meeting these requirements include stacks formed variously of titanium (“Ti”), nickel-vanadium (“NiV”), copper (“Cu”), aluminum (“Al”), chromium (“Cr”), and chromium-copper (“CrCu”), as follows: Ti/NiV/Cu, Al/NiV/Cu, Cr/CrCu/Cu, Ti/Cu and Cr/Cu. Layers of gold (“Au”), in addition, are optional. Typically, the UBM metals are deposited not only on the exposed target terminals, but as well on the polymer insulation layers (e.g., polyimide, benzocyclobutene (“BCB”), or polybenzoxazole (“PBO”)), that form a surface passivation layer on the die.
To form the UBM pads on a substrate, such as a die, two methods are commonly used. One is the lift-off technique. The other is the etch-back process.
The lift-off technique requires accurate control of the deposition temperature of the UBM metals because the photoresist that is initially deposited typically cannot stand high temperatures over 150° C. Such temperatures can easily be exceeded during deposition of the UMB metals onto the photoresist. In addition, the shadow effect of the lift-off process requires a thicker metal deposition, therefore also requiring a longer deposition process time. Typically, high pressure scrubbing is also required to clean the substrate surface after stripping of the photoresist. Therefore, the etch-back process is commonly used rather than the lift-off technique.
However, the etch-back process also has problems. For example, when the UBM metals are deposited on the insulation or surface passivation layer, the residual stress of individual metal layers must be controlled. Otherwise, high residual stress may cause the metal and underlying polymer to peel and crack during patterning of the UBM pads for the etch-back process. These defects may happen even earlier, just after the deposition of the UBM metal layers.
Of the candidate UBM metals, Cr and NiV are well known for their high residual stress. If the UBM structures of Ti/NiV/Cu and Cr/CrCu/Cu and the like are employed, the above defects are prone to happen. Additional process steps can sometimes be taken to deter the defects from happening, but at the expense of reduced throughput and increased production cost. In some applications, it may be possible to omit the barrier layer of NiV, but the barrier layer is needed under lead-free solder bumping because the large amount of tin (“Sn”) in the lead-free solder ball consumes the Cu intensively.
Another etch-back process problem has been encountered when a flip chip configuration has been adopted that utilizes both a peripheral array and a center area array at the same time for the flip chip interconnection. It has been desired in such configurations to have a bigger size for the solder balls in the peripheral array. If the difference between the two sizes of solder balls has not been significant, for example less than 100 μm, and the pitches between the UBM pads were big enough, both the bigger bumps and the smaller bumps could be formed on the substrate at the same time using electroplating or solder paste printing.
However, in other cases, the bigger bumps and smaller bumps (e.g., having over 100 μm bump height difference) could not be formed on the substrate at the same time because of the technical limits of the photoresist thickness and the pitches between the UBM pads. In this case, it was the practice to form smaller bumps only on the smaller substrate-like wafer or die. The bigger bumps were typically formed separately on the bigger, next level package substrate, such as a printed circuit board (“PCB”). Then, the smaller dies with the smaller bumps were mounted to the bigger, next level package. However, this caused production throughput to be reduced, and therefore, cost was increased.
In order to increase throughput and reduce cost, there thus remains a significant need to form both the bigger bumps and the smaller bumps, having over 100 μm bump height difference, on the larger substrate-like wafer with no more than one or two times of solder reflow.
Thus, a need still remains for reducing residual stress in flip chip UBM layers while simultaneously enabling the formation, on a single substrate, of multi-size solder bumps having considerable height differences. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.